16-09-2021

Vhdl Code For Serial Adder Using Finite State Machine

This tutorial is about implementing a finite state machine is vhdl. I will go through each and every step of designing a finite state machine and simulating it. Xilinx is used as a tool to construct finite state machine and for simulation and testing purpose. I suppose you know what is finite state machine and why it is used? I will give a short introduction of finite state machines and then move on to the designing phase.
  1. Vhdl Code For Serial Adder Using Finite State Machine
  2. Vhdl Code For Serial Adder Using Finite State Machine Designer
  3. Vhdl Code For Serial Adder Using Finite State Machine Diagram
  4. Vhdl Code For Serial Adder Using Finite State Machine Calculator
  5. 4 Bit Serial Adder
Finite state machine is a graphical model/representation of sequential activities or events. After representing and modeling the events they can be implemented easily in case of sequential logic designs.
Finite state machines can be utilized in many fields of study e.g neural networks, artificial intelligence, mathematics, games, robotics and sequential flow of data. Since we are dealing with the sequential circuits so i will explain their use in sequential circuit design in this tutorial.
There are many fsm(finite state machines) in existence. The two most popular used in digital combinational and sequential circuits are Vhdl code for serial adder using finite state machines
  • Melay Machine
  • Moore Machine
The main difference between melay and moore is the computation of the next state. In melay machine the output depends on the current state and the input variables. Where as in moore machine the output depends on the current state only. There are also other differences which are hardly highlighted any where.
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Register the block diagram is attached, vhdl code for serial adder using moore type fsm serial adder verilog 4 bit serial adder when doing digital system design it is very common to begin by defining how the system works with a finite state machine model this design step allows the designer to think. Keywords— D-latch, Finite state machine, Mealy Model, Multisim, Serial adder. INTRODUCTION TO FINITE STATE MACHINE Based on the state table we can construct the state diagram. The state diagram is as shown in Fig 2. As observed in the state A finite state machine can be represented by a state transition table or a state diagram.


Moore Machine
  1. More number of states in moore compared to melay for same fsm.
  2. States changes after 1 clock cycle. Latency = 1.
  3. Synchronous output. Because the states are determined in a process.
  4. States are output.

Mealy Machine

  1. Less number of states in mealy compared to moore for same fsm.
  2. State transition on the same clock cycle. Latency = 0.
  3. Asynchronous output.
  4. Transition are output.
In the below figure you can see a melay machine fsm. Fsm has four states S0, S1, S2 and S3. Outputs can be seen on the edges. Inputs are also on the edges. Transitions from one state to another take place on the bases of current state and the inputs. Fsm below is actually a counter. When input is 1 the state moves to next and when the input is 0 state jumps to previous. Counter is 4-bit but only one bit is manipulated in the counter. ‘1’ in the 4-bit output moves forward or backward depending on the state and input.
The top level entity of melay machine fsm is below. Output is 4-bit named count. Clock and reset are necessary signals for finite state machine. UpDw is a single bit input. When UpDw is 1 state jumps from current to next and when 0 it scroll back to previous state.

Vhdl Code For Serial Adder Using Finite State Machine

Vhdl Code For Serial Adder Using Finite State Machine
Melay machine fsm counter – vhdl top level entity
Output of the melay machine can be seen in the figure below. If you match the behavior of the simulation with the actual state machine above you will find the behavior of the two similar. Which means that the finite state machine is implemented correctly. The simulation below is run on ISim simulator by xilinx.
Filed Under: Microcontroller Projects, VHDL

A state machine is a sequential circuit that advances through a number of states. To describe a state machine in Quartus II VHDL, you can declare an enumeration type for the states, and use a Process Statement for the state register and the next-state logic.

Vhdl Code For Serial Adder Using Finite State Machine Designer

The VHDL example shown below implements a 3-state state machine.

Vhdl Code For Serial Adder Using Finite State Machine

This state machine includes a Process Statement that is activated on every positive edge of the clk control signal for the next-state logic, and a Process Statement that is activated on a change in the state variable. This state machine has an asynchronous reset, which the Compiler recognizes.

Vhdl Code For Serial Adder Using Finite State Machine Diagram

Note: The Compiler also recognizes state machines with a synchronous reset.

The signal state stores the current state of the state machine. The declaration of the type STATE_TYPE defines the states s0, s1, and s2 for state_machine.

At startup, the state machine is initialized to the reset state. If there is no reset state, the state machine is initialized to the first state in the Type Declaration. Otherwise, the first Case Statement determines the transitions between the states (that is, which state to enter on the next rising edge of clk) and the second Case Statement determines the value of the outputs for each state.

Vhdl Code For Serial Adder Using Finite State Machine Calculator

The Compiler recognizes state machines and reports them as such in the State Machines section of the Report window only if all of the following conditions are met:

  • The type of the signal or variable that represents the state machine must be an enumerated type.

  • The Process Statement that describes the state machine must be clocked, and must contain an If Statement that checks for a positive edge of the clk control signal.

  • The state machine behavior, that is, the next-state logic, is defined with Case Statements at the top level.

  • All assignments to the signal or variable that represents the state machine are within the process.

  • The state machine must have more than two states. Instant immersion english software, free download.

VHDL state machines that do not meet these conditions are converted into logic gates and registers that are not listed as state machines in the Report window. The Compiler also converts VHDL state machines to 'regular' logic when the ENUM_ENCODING attribute is used to manually specify state assignments in a project.

Note: Because the Compiler usually produces the best results, Altera recommends that you do not use the ENUM_ENCODING attribute, but instead allow the Compiler to recognize and encode the state machine.

4 Bit Serial Adder

You can assign states in the following ways:

For more information, refer to the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

  • Section 8.1: Wait Statement

  • Section 8.6: If Statement

  • Section 8.7: Case Statement

  • Section 9.2: Process Statement